The present invention relates generally to design automation, and relates more particularly to parallel processing of very large-scale complex semiconductor chip designs.
Design automation has conventionally been performed using computer software executed on a single processor, usually in a “flat” fashion where an entire semiconductor chip design is processed at the same level at once. Although this may achieve good semiconductor chip quality through global consideration of the entire semiconductor chip design, the process is clearly limited by the speed and power of the single computer used for processing.
By contrast, each processor in a parallel processing scheme sees only a portion of the entire semiconductor chip design after partitioning. Such a processing scheme makes the accommodation of engineering changes more complicated, however, because modifications in one partition will likely affect the partition's timing behavior and, in turn, ripple the effect to other partitions. Thus, a local change may entail a more global (and potentially unpredictable and negative) impact on the semiconductor chip design. This would defeat the purpose of the parallel processing scheme.
Thus, there is a need in the art for a method and apparatus for parallel processing of semiconductor chip designs.